Toshiba cuts phase noise in oscillation ICs for wireless communication
Technology ( 6 )
TOKYO —
Toshiba Corp has developed noise reduction technology that reduces jitter in radio-frequency signals, cutting phase noise by up to 90%. This breakthrough opens the way for a further migration to high-speed wireless communication chips for wireless LAN and WiMAX.
Radio frequency phased locked loops (PLL) in mobile communication LSI chips were typically structured with analog and digital circuits. As achieving ultra-fine analog circuits is highly challenging, there is now a shift to all digital PLL using time-to-digital converters (TDC). While digitization reduces circuit size it also increases phase noise—a degrading displacement in the pulse of a radio frequency signal—due to larger delay in the TDC’s inverter circuits.
Cutting phase noise is essential for high speed communication standards, like WiMAX, which require highly accurate signals. There is the concern that current TDC is sensitive to variations in manufacturing processes that impact on their performance. This raises a need for more robust manufacturability.
To reduce susceptibility variations in mass production and suppress phase noise, Toshiba developed a new TDC integrating interpolation circuits that use a low resistance conductor to connect the output of two inverters. A triple interpolation splits the cycle of output signal of frequency synthesizers, and reduces phase noise by 90%.
This solution successfully achieves a PLL with stable performance, as it utilizes a stable waveform from the PLL itself as a reference time interval for converting time to digital data, not the delay time of the inverters.
In a test chip manufactured with 65nm CMOS process, phase noise was reduced to -104dBc/Hz, 90% lower than that of the previous all digital PLL that Toshiba announced at ISSCC2011. Chip size was cut to 0.18 mm2, approximately 80% smaller than the analog PLL in a mobile WiMAX transceiver chip.
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0
electric2004
Reducing phase noise is basically a question of effort. Lets put it another way: finally Toshiba has improved his circuits, which were before lacking performance compared to competitors.
0
FlatLight
What kind of effort do you mean here? design time effort? Their concern is very simple: how to achieve low phase noise while reducing power and chip area. Design effort is just not important at all for such a mass production building block.
If you have been following the trend, as correctly pointed out in the press release, basically there is a shift from the analog PLL, using phase/frequency detectors, charge pump, and loop filter, towards all-digital designs. In the latter, time-to-digital converters (TDCs) are key building blocks. Apparently, I should go over the ISSCC paper to be sure, they have come up with a new TDC topology that performs considerably better than previously.
Are you sure about this statement? Have you really looked at the phase noise, chip area and power figures?
0
electric2004
Let me give you a conservative answer:
In order to measure the given -104dBc/Hz, one needs a measurement instrument, for example a spectrum analyzer, where the combination of local oscillator and mixer has a better phase noise than the system to be measured. In other words, inside such spectrum analyzers (for example from Agilent, Tektronix or Rhode and Schwarz) there needs to be a local oscillator or synthesizer with higher quality. And yes, these companies put a lot of effort in it.
Standard analyzer models obtain also in the order of 100dBc/Hz, while top models achieve in the order of 130dBc/Hz.
The point for Toshiba is, that they were able to put their effort into a small chip, which will give performance at low cost.
The real problem behind this, is the ever more shrinking of the structures to be put on silicon, which results in building blocks, which had performed well, when the chip structures were larger, now needing a re-design.
A remember very well the nice features of GaAs based chips for high frequency applications. But they are not cost competitive for the mass market, which is supplied by silicon based devices.
1
FlatLight
Yes, I think you missed the point of the original press release. You should not compare the results recently achieved by Toshiba with the performance of high-end spectrum analyzers made by Agilent, Tektronix, and the like.
You should be comparing Toshiba with Broadcom, Marvel, TI, etc. Those are the providers of wireless chipsets for mass markets. The companies you listed are just makers of high-end electronic equipment whose cost and power consumption are just not important at all.
Indeed, CMOS is still king in this field.
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electric2004
You can find the abstract of Toshiba at:
http://www.vlsisymposium.org/circuits/cir_abstract/11-2.htm
But the information is not more than in the JT article.
0
electric2004
And there, MARVEL claims:
in-band noise floor is -108 dBc/Hz
http://www.vlsisymposium.org/circuits/cir_abstract/11-1.htm
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